/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
 * Copyright 2023 NXP
 */

#ifndef S32G_GPR_NVMEM_H
#define S32G_GPR_NVMEM_H

#define S32G_GPR_PFE_EMACS_INTF_SEL_OFFSET	0x80
#define S32G_GPR_PFE_COH_EN_OFFSET              0x81
#define S32G_GPR_PFE_PWR_CTRL_OFFSET            0x82
#define S32G_GPR_PFE_EMACS_GENCTRL1_OFFSET      0x83
#define S32G_GPR_PFE_GENCTRL3_OFFSET            0x84

#define S32G_GPR_CELL_SIZE			0x4

#endif
